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2131 Uniform Subcomputations The first point of pipelining idealism states that the computation to be pipelined can be evenly partitioned into it uniformlatency subcomputations This means that the original design can be evenly partitioned into k balanced (ie, having the same latency) pipeline stages If the latency of the original computation, and hence the clocking period of the nonpipelined design, is T, then the clocking period of a it-stage pipelined design is exactly T/k, which is the latency of each of the k stages Given this idealized assumption, the M o l d increase in throughput is achieved due to the it-fold increase of the clocking rate This idealized assumption may not be true in an actual pipelined design It may not be possible to partition the computation into perfectly balanced stages We see in our floating-point multiplier example that the latency of 400 ns of the original computation is partitioned into three stages with latencies of 123, ISO, and 123 ns, respectively Clearly the original latency has not been evenly partitioned into three balanced stages!" Since the clocking period of a pipelined design is d i c ^ tated by the stage with the longest latency, the stages with shorter latencies in effect will incur some inefficiency or penalty^n our example, the first and third stages have an inefficiency of 25 ns each; we called such inefficiency within pipeline stages, the internal fragmentation of pipeline stages Because of such internal fragmentation,lhetotal latency required for performing the same computation will increase from T to 7}, and the clocking period of the pipelined design will be no longer T/k but Tf/k In our example the performance of the three subcomputations will require 450 ns instead of the original 400 ns, and the clocking period will be not 133 ns (400/3 ns) but 150 ns There is a secondary implicit assumption, namely, that no additional delay is introduced by the introduction of buffers between pipeline stages and that no additional delay is required for ensuring proper clocking of the pipeline stages Again, A this assumption may not be true in actual designs In our example, an additional T 22 ns is required to ensure proper clocking of the pipeline stages, which resulted in the cycle time of 172 ns for the three-stage pipelined design The ideal cycle time for a three-stage pipelined design would have been 133 ns The difference between 172 and 133 ns for the clocking period accounts for the shortfall from the idealized three-fold increase of throughput The first point of pipelining idealism basically assumes two things: (1) There is no inefficiency introduced due to the partitioning of the original computation into multiple subcomputations; and (2) there is no additional delay caused by the introduction of the interstage buffers and the clocking requirements In chip-level design the additional delay incurred for proper pipeline clocking can be minimized by employing latches similar to the Earle latch The partitioning of a computation into balanced pipeline stages constitutes the first challenge of pipelined design The goal is to achieve stages as balanced as possible to minimize internal fragmentation Internal fragmentation due to imperfectly balanced pipeline stages is the primary cause of deviation from the first point of pipelining idealism This deviation becomes a form of pipelining overhead and leads to the shortfall from the idealized M o l d increase of throughput in a it-stage pipelined design. rdlc pdf 417 PDF417 Barcode Creating Library for RDLC Reports | Generate ...
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